1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of setting a surface height of a film, which is filled in a trench provided to a semiconductor substrate, to a position of a desired depth from an opening of the trench.
2. Description of the Related Art
The development of a high-integrated semiconductor device has been recently accelerated. As one of the approaches, it has been examined to adopt a vertical MOS transistor. For example, JP-A No. 2008-4915 (Patent Document 1) discloses a technology in which first and second source/drain areas are formed in upper and lower portions of a fin formed by a trench provided on a surface of a silicon substrate and a conductive material layer is provided to side faces of the trench via a dielectric layer, thereby forming a gate electrode. According to the technology, it is possible to reduce an area occupied by a memory cell by a half or less and to thus obtain a high-integrated NAND flash memory array.
However, in Patent Document 1, after the dielectric layer and the conductive material layer are deposited on a whole surface of the substrate having the trench formed thereto, an etching-back is performed as it is. Thus, sidewall gates are separately formed at both sides of the trench.
In general, it is necessary to reduce a parasitic capacity between a source/drain and a gate, which occurs at overlapped portions of a source/drain area and sidewall gate electrodes formed at an upper portion of silicon pillar. Accordingly, a height of an upper end of the sidewall gate electrode of a vertical MOS transistor formed to the pillar-type silicon should be lower than a height of an upper end of the silicon pillar, i.e., a height of a trench opening by a predetermined distance. Due to this, the etching-back for the conductive material layer should be performed in such a way that over-etching is continuously performed even after the sidewall gate electrodes at both sides of the trench are separated, thereby making a height of an upper end of the sidewall gate electrode be a predetermined height. The over-etching is hardly controllable because the etching is unusually progressed not only on the upper end of the sidewall gate electrodes but also on the side surfaces of the sidewall gate electrodes, so that a partially thinned portion is generated by irregularly progressing side etching or heights of the sidewall gate electrodes become non-uniform.